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U4091BM
Programmable Telephone Audio Processor
Description
The programmable telephone audio processor U4091BM is a linear integrated circuit for use in feature phones, answering machines and fax machines. It contains the speech circuit, tone-ringer interface with DC/DC converter, sidetone equivalent and ear-protection rectifiers. The circuit is line-powered and contains all components necessary for signal amplification and adaptation to the line. The U4091BM can also be supplied via an external power supply. An integrated voice switch with loudspeaker amplifier enables hands-free or loudhearing operation. With an anti-feedback function, acoustical feedback during loudhearing can be reduced significantly. The generated supply voltage is suitable for a wide range of peripheral circuits.
Features
D Speech circuit with anti-clipping D Tone-ringer interface with DC/DC converter D Speaker amplifier with anti-distortion D Power-supply management (regulated, unregulated)
and a special supply for electret microphone
Benefits
D No piezoelectric transducer for tone ringing necessary D Complete system integration of analog signal processing on one chip
D Very few external components
D Voice switch D Interface for answering machine and cordless phone
Applications
Feature phone, answering machine, fax machine, speaker phone, cordless phone
Block Diagram
Speech circuit
Voice switch
Audio amplifier
Clock Data Reset
Serial bus DTMF Tone ringer
14601
MCU
Ordering Information
Extended Type Number U4091BM-AFN U4091BM-AFNG3 Package SSO44 SSO44 Remarks Taped and reeled
Rev. A1, 02-Jun-98
1 (29)
Target Specification
Detailed Block Diagram
U4091BM
VL
2 (29)
2 TXACL 5 STBAL 4 43 44 1 39 42 38
AGATX
9
10
8 17 15
Power supply
16 12
3 V MIC
MICRO AGARX TXA
11 30 Offset canceler DTMF/ melody Filter Offset canceler MUX
MIC
Target Specification
Rev. A1, 02-Jun-98
Figure 1. Detailed block diagram
22
40
Ringing power converter
21 19 20 V RING
AGCO
AMPB
LRX
DTMF
ADC
AGC
AGCI AMREC
Switch matrix
EPO RXLS LTX LIDET VMP RFDO
41 7 6 18 REG POR
RA SACL SA 14 13 AFS control 35 34 37 36 33 31 32 BIDIR serial bus 24 25 23
DIV.
1/8/16/32
OSC.
3.58 MHz
26
27 29 28
mC
14572
RECO1
MICO
V MP
U4091BM
Pin Description
Pin 1 2 3 4 Symbol Function RECIN Receive amplifier input TXACL Time-constant adjustment for transmit anti-clipping MIC3 Microphone input for hands-free operation MIC2 Input of symmetrical microphone amplifier with high common-mode rejection ratio MIC1 Input of symmetrical microphone amplifier with high common-mode rejection ratio RECO2 Output of the receive amplifier RECO1 Output of the receive amplifier, also used for sidetone network IND The internal equivalent inductance of the circuit is proportional to the value of the capacitor at this pin. A resistor connected to ground may be used to adjust the DC mask. VL Positive supply-voltage input to the device in speech mode SENSE Input for sensing the available line current GND Ground, reference point for DC- and AC signals VB Unstabilized supply voltage for speech network SAO2 Negative output of speaker amplifier (push-pull only) SAO1 Positive output of speaker amplifier (single ended and push-pull operation) VMPS Unregulated supply voltage for the microcontroller (via series regulator to VMP) VMP Regulated output voltage for supplying the microcontroller (typ. 3.3 V/ 6 mA in speech mode) VMIC Reference node for microphone amplifier, supply for electret microphones TSACL Time constant for speaker amplifier anti-clipping Pin 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 Symbol VRING IMPA COSC SWOUT INT SCL SDA OSCIN
OSCOUT
5
6 7 8
RESET ES ADIN BNMR BNMT CT TLDR INLDR INLDT TLDT IMPSW MICO AMPB AMREC STO STC STRC
9 10 11 12 13 14
15
16
17
Function Input for ringer supply Input for adjusting the ringer input impedance 70-kHz oscillator for ringing power converter Output for driving the external switch resistor Interrupt line for serial bus Clock input for serial bus Data line for serial bus Input for 3.58-MHz oscillator Clock output for the microcontroller Reset output for the microcontroller Input for external supply indication Input of A/D converter Output of background-noise monitor receive Output of background-noise monitor transmit Time constant for mode switching of voice switch Time constant of receive-level detector Input of receive-level detector Input of transmit-level detector Time constant of transmit-level detector Switch for aditional line impedance Microphone preamplifier output Input for playback signal of answering machine Output for recording signal of answering machine Output for connecting the sidetone network Input for sidetone network Input for sidetone network
18
Remark: The protection device at Pin RECIN is disconnected.
Rev. A1, 02-Jun-98
3 (29)
Target Specification
U4091BM
RECIN TXACL MIC3 MIC2 MIC1 RECO2 RECO1 IND VL SENSE GND VB SAO2 SAO1 VMPS VMP VMIC TSACL VRING IMPA COSC SWOUT 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22
14751
44 43 42 41 40 39 38 37 36 35 34 33 32
STRC STC STO AMREC AMPB MICO IMPSW TLDT INLDT INLDR TLDR CT BNMT
DC Line Interface and Supply-Voltage Generation
The DC line interface consists of an electronic inductance and a dual-port output stage which charges the capacitors at VMPS and VB. The value of the equivalent inductance is given by: L=2 RSENSE CIND (RDC R30) / (RDC + R30)
The U4091BM contains two identical series regulators which provide a supply voltage VMP of 3.3 V suitable for a microprocessor. In speech mode, both regulators are active because VMPS and VB are charged simultaneously by the DC line interface. The output current is 6 mA. The capacitor at VMPS is used to provide the microcomputer with sufficient power during long line interruptions. Thus, long flash pulses can be bridged or an LCD display can be turned on for more than 2 seconds after going on-hook. When the system is in ringing mode, VB is charged by the on-chip ringing power converter. In this mode, only one regulator is used to supply VMP with maximum 3 mA.
Supply Structure of the Chip
A main benefit of the U4091BM is the easy implementation of various applications due to the flexible system structure of the chip. Possible applications:
31 BNMR 30 ADIN 29 ES 28 RESET
D Group listening phone D Hands-free phone D Phones which feature ringing with the built-in speaker
amplifier
D Answering machine with external supply
The special supply topology for the various functional blocks is illustrated in figure 3. There are four major supply states:
27 OSCOUT 26 OSCIN 25 SDA 24 23 SCL INT
1. 2. 3. 4.
Speech condition Power down (pulse dialing) Ringing External supply
Figure 2. Pinning
1. In speech condition, the system is supplied by the line current. If the LIDET-block detects a line voltage above approximately 2 V, the internal signal VLON is activated. This is detected via the serial bus, all the blocks which are needed have to be switched on via the serial bus.
4 (29)
Rev. A1, 02-Jun-98
Target Specification
U4091BM
For line voltages below 2 V, the switches remain in quiescent state as shown in the diagram. 2. When the chip is in power-down mode (Bit LOMAKE), e.g., during pulse dialing, all internal blocks are disabled via the serial bus. In this condition, the voltage regulators and their internal bandgap are the only active blocks. 3. During ringing, the supply for the system is fed into VB via the Ringing Power Converter (RPC). Normally, the speaker amplifier in single-ended mode is used for ringing. The frequency for the melody is generated by the DTMF/Melody generator. 4. In an answering machine, the chip is powered by an external supply via Pin VB. The answering machine connections can be directly put to U4091BM. The answering machine is connected to the Pin AMREC. For the output AMREC, an AGC function is selectable via the serial bus. The output of the answering machine will be connected to the Pin AMPB, which is directly connected to the switching matrix, and thus enables the signal to be switched to every desired output.
Ringing Frequency Detector (RFD)
The U4091BM provides an output signal for the microcontroller. This output signal is always double the value of the input signal (ringing frequency). It is generated by a current comparator with hysteresis. The levels for the on-threshold are programmable in 16 steps; the off-level is fixed. Every change of the comparator output generates a high level at the interrupt output INT. The information can then be read out by means of a serial bus with either normal or fast read mode. The block RFD is always enabled.
VL RSENSE 10 C 1 F IND R + - R 300 k V 220F
14573
5.5 V
VMPS 470F
- + + - 3.3 V VMP 47 F VB
5.5 V
Figure 3. Supply generator
Ringing Power Converter (RPC)
The RPC transforms the input power at VRING (high voltage/ low current) into an equivalent output power at VB (low voltage/ high current) which is capable of driving the low-ohmic loudspeaker. The input impedance at VRING is adjustable from 3 kW to 12 kW by RIMPA (ZRING = RIMPA / 100) and the efficiency of the stepdown converter is approximately 65%.
Rev. A1, 02-Jun-98
Target Specification
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Clock Output Divider Adjustment
The Pin OSCOUT is a clock output which is derived from the crystal oscillator. It can be used to drive a microcontroller or another remote component and thereby reduces the number of crystals required. The oscillator frequency can be divided by 1, 8, 16, 32. During power-on reset, the divider will be reset to 1 until it is changed by setting the serial bus. CLK[0:1] 0 1 2 3 Divider 1 8 16 32 Frequency 3.58 MHz 447 kHz 224 kHz 112 kHz
RINGTH[0:3] 0 15 step
VRING 7V 22 V 1V
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Serial Bus Interface
The circuit is controlled by an external microcontroller through the serial bus. The serial bus is a bi-directional system consisting of a one-directional clock line (SCL) which is always driven by the microcontroller, and a bi-directional data-signal line. It is driven by the microcontroller as well as from the U4091BM (see fig. 23). The serial bus requires external pull-up resistors as only pull-down transistors (Pin SDA) are integrated. WRITE: The data is a 12-bit word: A0 - A3: address of the destination register (0 to 15) D0 - D7: content of the register The data line must be stable when the clock is high. Data must be shifted serially. After 12 clock periods, the write indication is sent. Then, the transfer to the destination register is (internally) generated by a strobe signal transition of the data line when the clock is high. 5 (29)
U4091BM
READ: There is a normal and a fast-read cycle. In the normal read cycle, the microcontroller sends a 4-bit address followed by the read indicator, then an 8-bit word is read out. The U4091BM drives the data line. The fast read cycle is indicated by a strobe signal. With the following two clocks the U4091BM reads out the status bits RFDO and LIDET which indicate that a ringing signal or a line signal is present (see figures 4, 5 and 6). 0 1 2 3 DTMFF[2:3] in DTMF Mode 00 01 10 11 Frequency Error / %
DTMF Dialing
The DTMF generator sends a multi-frequency signal through the matrix to the line. The signal is the result of the sum of two frequencies and is internally filtered. The frequencies are chosen from a low and a high frequency group. The circuit conforms to the CEPT recommendation concerning DTMF option.
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Two different levels for the low level group and two different pre-emphasis (2.5 dB and 3.5 dB) can be chosen by means of the serial bus (rec. T/CF 46-03).
Melody - Confidence Tone Generation
Melody/confidence tone frequencies are given in the table below.
The frequencies are provided at the DTMF input of the switch matrix. A sinus wave, a square wave or a pulsed wave can be selected by the serial bus. Square signal means the output is half of frequency cycle high and half low. Pulsed signal means between the high and low phases are high impedance phases of 1/6 of the period. 0 1 2 3 4 5 6 7 DTMFM[0:2] 000 001 010 011 100 101 110 111 DTMF generator OFF Confidence tone melody on (sinus) Ringer melody (pulse) Ringer melody (square signal) DTMF (high level) DTMF (low level)
0 1 2 3
DTMFF[0:1] in DTMF Mode 00 01 10 11
Frequency
Error / %
697 770 852 941
-0.007 -0.156 0.032 0.316
6 (29)
Target Specification
AAAAA A A A AAAAAAAAAAAAAAAA AAA AAAAA A A AAAAA A A A A AAAAAAAAAAAAAAAA AAAAAAAAAAAA AA AAAAAAAAAAAAAAAA AAAAAAAAAAAA AA AAAAAAAAAAAAAAAA AAAAAAAAAAAA AA
1209 1336 1477 1633 -0.110 0.123 -0.020 -0.182 DTMFF4 in DTMF mode Pre-Emphasis Selection 0 2.5 dB 1 3.5 dB
DTMFF [0:4] 0 00000 1 00001 2 00010 3 00011 4 00100 5 00101 6 00110 7 00111 8 01000 9 01001 10 01010 11 01011 12 01100 13 01101 14 01110 15 01111 16 10000 17AAA 10001 18 10010 19 10011 20 10100 21 10101 22AAA 10110 23 10111 24 11000 25 11001 26 11010 27 11011 28 11100 29 11101 30 11110 31 11111 f Hz 440.0 466.2 493.9 523.2 554.4 587.3 622.3 659.3 698.5 740.0 784.0 830.0 880.0 932.3 987.8 1046.5 1108.7 1174.7 1244.5 1318.5 1396.9 1480.0 1568.0 1661.2 1760.0 1864.6 1975.5 2093.0 2217.5 2349.3 2663.3 2983.0 ToneName a1 b1 h1 c2 des2 d2 es2 e2 f2 ges2 g2 as2 a2 b2 h2 c3 des3 d3 es3 e3 f3 ges3 g3 as3 a3 b3 h3 c4 des4 d4 Error/% DTMF Key 1 4 7 * 2 5 8 0 3 6 9 # A B C D 1 4 7 * 2 5 8 0 3 6 9 # A B C D -0.008 697 1209 -0.016 770 1209 -0.003 852 1209 0.014 941 1209 0.018 697 1336 -0.023 770 1336 -0.129 852 1336 0.106 941 1336 -0.216 697 1477 -0.222 770 1477 0.126 852 1477 -0.169 941 1477 0.288 697 1633 -0.014 770 1633 -0.004 852 1633 -0.335 941 1633 -0.355 697 1209 -0.023AAA 770 1209 -0.129 852 1209 0.106 941 1209 -0.214 697 1336 -0.222 770 1336 0.126 852 1336 -0.241 941 1336 -0.302 697 1477 -0.014 770 1477 0.665 852 1477 0.367 941 1477 0.387 697 1633 0.771 770 1633 --- 852 1633 --- 941 1633
Rev. A1, 02-Jun-98
U4091BM
Write cycle
CLOCK
DATA
D7
D6
D5
D4
D3
D2
D1
D0
A3
A2
A1
A0 R/W=0 Strobe fromP
Data fromP
14574
Figure 4. Write cycle
Normal read cycle
CLOCK
DATA
A3
A2
A1
A0
R/W=1 Strobe fromP
D7
D6
D5
D4
D3
D2
D1
D0
14575
Data fromP
Data from U4091B
Figure 5. Normal read cycle
Fast read cycle
CLOCK
DATA Strobe from P
D7=IZC D6=IVE
Data from U4091B
14576
Figure 6. Fast read cycle
Rev. A1, 02-Jun-98
7 (29)
Target Specification
U4091BM
Table 1. Names and functions of the serial bus registers Register Group No Name R0 Enables R0B0 ENRING R0B1 ERX R0B2 ETX R0B3 ENVM R0B4 ENMIC R0B5 ENSTBAL R0B6 MUTE R0B7 ENRLT R1 Enables R1B0 ENSACL R1B1 ENSA R1B2 ENSAO R1B3 ENAM R1B4 ENAGC R1B5 free R1B6 free R1B7 FOFFC R2 Matrix R2B0 I1O1 R2B1 I1O2 R2B2 I1O3 R2B3 I1O4 R2B4 I1O5 R2B5 I2O1 R2B6 I2O2 R2B7 I2O3 R3 Matrix R3B0 I2O4 R3B1 I2O5 R3B2 I3O1 R3B3 I3O2 R3B4 I3O3 R3B5 I3O4 R3B6 I3O5 R3B7 I4O1 R4 Matrix R4B0 I4O2 R4B1 I4O3 R4B2 I4O4 R4B3 I4O5 R4B4 I5O1 R4B5 I5O2 R4B6 I5O3 R4B7 I5O4 R5 AGATX R5B0 free MICLIM R5B1 AGATX0 R5B2 AGATX1 R5B3 AGATX2 R5B4 MICHF R5B5 DBM5 R5B6 MIC0 R5B7 MIC1 Description Enable ringer Enable receive part Enable transmit part Enable VM-generator Enable microphone Enable sidetone Muting earpiece amplifier Enable POR low threshold Enable anti-clipping for speaker amplifier Enable speaker amplifier and AFS Enable output stage speaker amplifier Enable answering machine connections Enable AGC for answering machine Status 1 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Speed up offset canceller Switch on MIC / LTX Switch on MIC / SA Switch on MIC / EPO Switch on MIC / AMREC Switch on MIC / AGCI Switch on DTMF / LTX Switch on DTMF / SA Switch on DTMF / EPO Switch on DTMF / AMREC Switch on DTMF / AGCI Switch on LRX / LTX Switch on LRX / SA Switch on LRX / EPO Switch on LRX / AMREC Switch on LRX / AGCI Switch on AMPB / LTX Switch on AMPB / SA Switch on AMPB / EPO Switch on AMPB / AMREC Switch on AMPB / AGCI Switch on AGCO / LTX Switch on AGCO / SA Switch on AGCO / EPO Switch on AGCO / AMREC Gain transmit AGA LSB Gain transmit AGA Gain transmit AGA MSB Select RF-microphone input Max. transmit level for anti-clipping Gain microphone amplifier LSB Gain microphone amplifier MSB
8 (29)
Rev. A1, 02-Jun-98
Target Specification
U4091BM
Register R6 Group Shut down Sidetone No R6B0 R6B1 R6B2 R6B3 R6B4 R6B5 R6B6 R6B7 R7B0 R7B1 R7B2 R7B3 R7B4 R7B5 R7B6 R7B7 R8B0 R8B1 R8B2 R8B3 R8B4 R8B5 R8B6 R8B7 R9B0 R9B1 R9B2 R9B3 R9B4 R9B5 R9B6 R9B7 R10B0 R10B1 R10B2 R10B3 R10B4 R10B5 R10B6 R10B7 R11B0 R11B1 R11B2 R11B3 R11B4 R11B5 R11B6 R11B7 Name SD free SL0 SL1 LF0 LF1 LF2 LF3 P0 P1 P2 P3 P4 AGARX0 AGARX1 AGARX2 EA0 EA1 EA2 EA3 EA4 IMPH LOMAKE AIMP AFS0 AFS1 AFS2 AFS3 AFS4 AFS5 AFS4PS free SA0 SA1 SA2 SA3 SA4 SE LSCUR0 LSCUR1 ADC0 ADC1 ADC2 ADC3 NWT SOC ADCR MSKIT Description Shut down Slope adjustment for sidetone LSB Slope adjustment for sidetone MSB Low frequency adjustment for sidetone LSB Low frequency adjustment for sidetone Low frequency adjustment for sidetone Low frequency adjustment for sidetone MSB Pole adjustment for sidetone LSB Pole adjustment for sidetone Pole adjustment for sidetone Pole adjustment for sidetone Pole adjustment for sidetone MSB Gain receive AGC LSB Gain receive AGC Gain receive AGC MSB Gain earpiece amplifier LSB Gain earpiece amplifier Gain earpiece amplifier Gain earpiece amplifier Gain earpiece amplifier MSB Line impedance selection (1 = 1 kW) Short circuit during pulse dialing Switch for additional external line impedance AFS gain adjustment LSB AFS gain adjustment AFS gain adjustment AFS gain adjustment AFS gain adjustment AFS gain adjustment MSB Enable 4-point sensing Gain speaker amplifier LSB Gain speaker amplifier Gain speaker amplifier Gain speaker amplifier Gain speaker amplifier MSB Speaker amplifier single-ended mode Speaker amplifier charge-current adjustment LSB Speaker amplifier charge-current adjustment MSB Input selection ADC Input selection ADC Input selection ADC Input selection ADC Network tuning Start of ADC conversion Selection of ADC range Mask for interrupt bits Status 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
R7
Sidetone AGARX
R8
EARA Line imp.
R9
AFS
R10
SA
R11
ADC
Rev. A1, 02-Jun-98
9 (29)
Target Specification
U4091BM
Register R12 Group DTMF No R12B0 R12B1 R12B2 R12B3 R12B4 R12B5 R12B6 R12B7 R13B0 R13B1 R13B2 R13B3 R13B4 R13B5 R13B6 R13B7 R14B0 R14B1 R14B2 R14B3 R14B4 R14B5 R14B6 R14B7 R15B0 R15B1 R15B2 R15B3 R15B4 R15B5 R15B6 R15B7 Name DTMFF0 DTMFF1 DTMFF2 DTMFF3 DTMFF4 DTMFM0 DTMFM1 DTMFM2 CLK0 CLK1 RTH0 RTH1 RTH2 RTH3 TME0 TME1 TME2 TME3 free CLOR0 CLOR1 CLOR2 CLOR3 CLOR4 free free free CLOT0 CLOT1 CLOT2 CLOT3 CLOT4 Description DTMF frequency selection DTMF frequency selection DTMF frequency selection DTMF frequency selection DTMF frequency selection Generator mode selection Generator mode selection Generator mode selection Selection clock frequency for mC Selection clock frequency for mC Ringer threshold adjustment LSB Ringer threshold adjustment Ringer threshold adjustment Ringer threshold adjustment MSB Test mode enable (low active) Test mode enable (high active) Test mode enable (high active) Test mode enable (low active) Adjustment for calculated receive log amp LSB Adjustment for calculated receive log amp Adjustment for calculated receive log amp Adjustment for calculated receive log amp Adjustment for calculated receive log amp MSB Status 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
R13
CLK RTH TM
R14
TM CLOR
R15
CLOT
Adjustment for calculated transmit log amp LSB Adjustment for calculated transmit log amp Adjustment for calculated transmit log amp Adjustment for calculated transmit log amp Adjustment for calculated transmit log amp MSB
Power-on Reset
To avoid undefined states of the system when it is powered on, an internal reset clears the internal registers. The system (U4091BM + microcontroller) is woken up by any of the following conditions: VMP > 2.75 V and VB > 2.95 V and line voltage (VL) or ringer (VRING) or external supply (ES) The power-down of the circuit is caused by a shut-down sent by the serial bus (SD = 1), low-voltage reset or by the watchdog function (see figures 8, 9 and 10).
Watchdog Function
To avoid the system operating the microcontroller in a wrong condition, the circuit provides a watchdog function. The watchdog has to be retriggered every second by triggering the serial bus (sending information to the IC or other remoted components at the serial bus). If there has been no bus transmission for more than one second, the watchdog initiates a reset. The watchdog provides a reset for the external mC, but does not change the U4091BM's registers.
10 (29)
Rev. A1, 02-Jun-98
Target Specification
U4091BM
Acoustic Feedback Suppression
Acoustical feedback from the loudspeaker to the handsfree microphone may cause instability of the system. The U4091BM has a very efficient feedback-suppression circuit which offers a 4-point- or alternatively a 2-pointsignal-sensing topology (see figure 7). Two attenuators (TXA and SAI) reduce the critical loop gain via the serial bus either in the transmit or in the receive path. The overall loop gain remains constant under all operating conditions. The LOGs produce a logarithmically-compressed signal of the TX- and RX-envelope curve. The block AFSCON determines whether the TX or the RX signal has to be attenuated. The voice-switch topology can be selected by the serial bus. In 2-point-sensing mode, AFSCON is controlled directly by the LOG outputs.
MICRO TXA MICO
AGATX
STO CTU RTU TLDT INLDT LOG LOG CALCT BNMT CTLO CBNMT
BNM Mode control BNM Line
AGARX LOG CALCR CT CCT AFSCON SA SAI
14577
LOG INLDR BNMR TLDR RRU CBNMR CRLO CRU RECO1 HV
DTD RECO2
Figure 7. Basic system configurations.
Rev. A1, 02-Jun-98
11 (29)
Target Specification
U4091BM
Line LID IVDD OSCOUT ton
VMP Reset trt - ton = 4.5 ms ton = start-up oscillator Figure 8. Power-on reset (line)
trt
14585
VRING VB IVDD VMP OSCOUT Reset ton trt Figure 9. Power-on reset (ringing)
14586
Line LID VMP LVI LVR
LVI Reset OSCOUT Figure 10. Power-on reset (low voltage reset)
14587
12 (29)
Rev. A1, 02-Jun-98
Target Specification
U4091BM
Dial-Tone Detector
The dial-tone detector is a comparator with one side connected to the speaker amplifier input and the other to VM with a 35-mV offset (see figure 11). If the circuit is in idle mode, and the incoming signal is greater than 35 mV (25 mVrms), the comparator's output will change disabling the receive idle mode. This circuit prevents the dial tone (which would be considered as continuous noise) from fading away as the circuit would have the tendency to switch to idle mode. By disabling the receive idle mode, the dial tone remains at the normally expected full level.
D The output of the receive log (LOGR)
- designated I2
D The output of the transmit background-noise monitor
(BNMT) - designated I3
D The output of the receive background-noise monitor
(BNMR) - designated I4
D The output of the dial-tone detector
The differential output (AFST, AFSR) of the block MODECON controls AFSCON. The effect of I1-I4 is as follows:
Background-Noise Monitors
This circuit distinguishes speech (which consists of bursts) from background noise (a relatively constant signal level). There are two background-noise monitors one for the receive path and the other for the transmit path. The receive background-noise monitor is operated on by the receive level detector, while the transmit background noise monitor is operated on by the transmit level detector (see figure 12). They monitor the background noise by storing a DC voltage representative of the respective noise levels in capacitors at CBNMR and CBNMT. The voltages at these pins have slow rise times (determined by the internal current source and an external C), but fast decay times. If the signal at TLDR (or TLDT) changes slowly, the voltage at BNMR (or BNMT) will remain more positive than the voltage at the noninverting input of the monitor's output comparator. When speech is present, the voltage at the non-inverting input of the comparator will rise quicker than the voltage at the inverting input (due to the burst characteristic of speech), causing its output to change. This output is sensed by the mode-control block.
*
4-Point Sensing
In 4-point sensing mode, the receive- and the transmitsensing path include additional CLOGs (Calculated Logarithmical amplifier). The block MODECON compares the detector output signals and decides whether receive-, transmit- or idle mode has to be activated. Depending on the mode decision, MODECON generates a differential voltage to control AFSCON. The MODECON block has seven inputs:
D The output of the transmit log (LOGT)
the comparison of LOGT, CLOGR
D The output of the receive clog (CLOGR)
- designated I1
D The output of the transmit clog (CLOGT)
the comparison of CLOGT, LOGR
Rev. A1, 02-Jun-98
Target Specification
AAAAAA A A A A AAAAAAAAAAAAAAAA AA AA AAAAAA A A A A AAAAAAAAAAAAAAAA AA AA AAAAAAAAAAAAAAAA AA AA AAAAAAAAAAAAAAAA AA AA AAAAAAAAAAAAAAAA AA AA AAAAAAAAAAAAAAAA AAAAAAAAAAA AAAAAA A A A AAAAAAAAAAAAAAAA AA AA AA AA AAAAAAAAAAAAAAAA AA AA AAAAAAAAAAAAAAAA AAAAAAAAAAA AAAAAAAAAAAAAAAA AA AA AAAAAA A A A AA AA AAAAAAAAAAAAAAAA AAAAAAAAAAA AAAAAAAAAAAAAAAA AA AA A AA AAAAAAAAAAAAAAAA AAAAAAAAAAA A AA
LOGT > CLOGR LOGT < CLOGR LOGR < CLOGT LOGR > CLOGT BNMT detects speech BNMT detects noise BNMR detects speech BNMR detects noise I1=T I1=R I2=T I2=R I3=S I3=N I4=S I4=N
Inputs Output I1 I2 I3 I4 Mode T T S X Transmit T R Y Y Change mode R T Y Y Change mode R R X S Receive T T N X Idle T R N N Idle R T N N Idle R R X N Idle X = don't care; Y = I3 and I4 are not both noise.
Term Definitions
1. `Transmit' means the transmit attenuator is fully on, and the receive attenuator is at maximum attenuation. 2. `Receive' means the receive attenuator is fully on, and the transmit attenuator is at maximum attenuation. 3. In `Idle' mode, the transmit- and receive attenuator are at the half of their maximum attenuation. a) `Change mode' means both transmit and receive speech are present in approximately equal levels. The attenuators are quickly switched (30 ms) to the opposite mode until one speech level dominates the other. b) `Idle' means speech has ceased in both transmit and receive paths. The attenuators are then slowly switched (1.5 seconds) to idle mode. 4. Switching to the full transmit or receive modes from idle mode is at the fast rate (30 ms).
13 (29)
U4091BM
Summary of the Truth Table
1. The circuit will switch to transmit mode if a) Both transmit level detectors sense higher signal levels than the respective receive level detectors and b) The transmit background-noise monitor indicates the presence of speech. 2. The circuit will switch to receive mode if a) Both receive level detectors sense higher signal levels than the respective transmit level detectors, and b) The receive background-noise monitor indicates the presence of speech. 3. The circuit will switch to the reverse mode if the level detectors disagree on the relative strengths of the signal levels, and at least one of the backgroundnoise monitors indicates speech. 4. The circuit will switch to idle mode when a) Both talkers are quiet (no speech present), or b) When one talker's speech level is continuously overridden by noise at the other speaker's location. The time required to switch the circuit between transmit, receive and idle is determined by internal current sources and the capacitor at Pin CT. A diagram of the CT circuitry is shown in figure 13. It operates as follows:
TLDR (TLDT) + - 56 k 33 k VM - + - + 36 mV I4 (I3) VB BNMR (BNMT) 1 F
D To switch to receive mode, IRX is turned on (ITX is
off), increasing the voltage on the capacitor to +240 mV with respect to VM.
D To switch to reverse mode, the current sources ITX,
IRX are turned off, and the current source IFI is switched on, discharging the capacitor to VM.
D To switch to idle mode, the current sources ITX, IRX,
IFI are turned off, and the current source ISI is charging the capacitor to VM.
IN
+ - 35 mV VM DTD
OUT I4 to mode control
14588
Figure 11. Dial tone detector
D CCT is typically 4.7 mF. D To switch to transmit mode, ITX is turned on (IRX is
off), charging the external capacitor to -240 mV below VM. (An internal clamp prevents further charging of the capacitor.)
14589
Figure 12. Background noise monitor
CT CCT I RX 10A I TX 10A IFI I SI
AFS control
to attenuators
Control circuit
4 I1-4
Dial tone det. VM VM
14590
Figure 13. Generation of control voltage (CT) for mode switching
14 (29)
Rev. A1, 02-Jun-98
Target Specification
U4091BM
TXA MICRO LOG
AFS control
Line
LOG SA SAI
14591
Figure 14. Block diagram hands-free mode U4091BM 2-point signal sensing
TXA MICRO LOGT CLOGT
BNMT
Mode control
BNMR
Line
CLOGR CT CCT AFS control SA SAI DTD
LOGR
14592
Figure 15. Block diagram hands-free mode U4091BM 4-point signal sensing
Rev. A1, 02-Jun-98
15 (29)
Target Specification
U4091BM
Analog-to-Digital Converter ADC
This circuit is a 7-bit successive approximation analogto-digital converter in switched capacitor technique. An internal bandgap circuit generates a 1.25-V reference voltage which is the equivalent of 1 MSB. 1LSB = 19.5 mV. The possible input voltage at ADIN is 0 to 2.48 V. The ADC needs an SOC (Start Of Conversion) signal. In the `High' phase of the SOC signal, the ADC is reset. 50 ms after the beginning of the `Low' phase of the SOC signal, the ADC generates an EOC (End Of Conversion) signal which indicates that the conversion is finished. The rising edge of EOC generates an interrupt at the INT output. The result can be read out by the serial bus. Voltages higher than 2.45 V have to be divided. The signal which is connected to the ADC is determined by 5 bits: ADC0, ADC1, ADC2, ADC3 and NWT. TLDR/TLDT measuring is possible relative to a preceding reference measurement. The current range of IL can be doubled by ADCR. If ADCR is `High', S has the value 0.5, otherwise S = 1. The source impedance at ADIN must be lower than 250 kW. Accuracy: 1 LSB + 3%
SOC 50 s EOC Figure 16. Timing of ADC
14594
IL
20mV/(1mA
S)
SOC
ADIN 0.4 VB 0.4 VMPS 0.75 VMP 8 8 (TLDR-REF) (TLDT-REF) 0.4 0.4 0.4 0.4 SAO1 OFF1 OFF2 OFF3 EOC
14595
MSB BIT5 BIT4
ADC
BIT3 BIT2 BIT1 LSB
Figure 17. ADC input selection Table 2. Input selection AD converter
AAAAAAAAAAAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AAAAAAAAAAAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAA A A
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16-31 OFF IL ADIN extern VB VMPS VMP TLDR TLDT free SAO1 Offcan1 Offcan2 Offcan3 free free free NWT (TLDR) I1 = S 127 mA D / 127 V2 = 2.5 V D / 127 (max. 2.5 V) V3 = (2.5 V / 0.4) D / 127 V4 = (2.5 V / 0.4) D / 127 V5 = (2.5 V / 0.75) D / 127 V6 = 8 (Vp - Ref) D / 127 V7 = 8 (Vp - Ref) D / 127 V4 = (2.5 V / 0.4) D / 127 TEMIC internal use TEMIC internal use TEMIC internal use D = measured digital word (0 < = D < = 127) S = programmable gain 0.5 or 1 Vp = peak value of the measured signal 16 (29) Rev. A1, 02-Jun-98
ADC[1:4] 00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111 1XXXX
Value
Target Specification
U4091BM
Switch Matrix
AGCO
AMPB LRX DTMF MIC Offset canceller Offset canceller I1
I5
I4
I3
I2
AGC
Lowpass O5 O4 O3 O2 O1 2.9 dB LTX AMREC EPO RXLS AGATX0 AGATX1 AGATX2 TXO -10 dB STO Figure 18. Diagram for switch matrix
14596
AGCI
Rev. A1, 02-Jun-98
Target Specification
AAAAAAAAA A A A AAAAAAAAAAAAAAAA AA A AAAAAAAAA A A A AAAAAAAAAAAAAAAA AA A AAAAAAAAAAAAAAAA AA A AAAAAAAAAAAAAAAA AA A AAAAAAAAAAAAAAAA AA A AAAAAAAAAAAAAAAA AA A AAAAAAAAAAAAAAAA AA A AAAAAAAAAAAAAAAA AA A AAAAAAAAAAAAAAAA AA A AAAAAAAAAAAAAAAA AA A AAAAAAAAAAAAAAAA AA A AAAAAAAAAAAAAAAA AA A AAAAAAAAAAAAAAAA AA A AAAAAAAAAAAAAAAA AA A AAAAAAAAAAAAAAAA AA A AAAAAAAAAAAAAAAA AA A AAAAAAAAAAAAAAAA AA A AAAAAAAAAAAAAAAA AA A AAAAAAAAAAAAAAAA AA A AAAAAAAAAAAAAAAA AA A AAAAAAAAAAAAAAAA AA A AAAAAAAAAAAAAAAA AA A AAAAAAAAAAAAAAAA AA A AAAAAAAAAAAAAAAA AA A AAAAAAAAAAAAAAAA AA A AAAAAAAAAAAAAAAA AA A AAAAAAAAAAAAAAAA AAAAAAAA AAAAAAAAAAAAAAAA AA A AAAAAAAAA A A AA A AAAAAAAAAAAAAAAA AA A AAAAAAAAAAAAAAAA AA A AAAAAAAAAAAAAAAA AA A AAAAAAAAAAAAAAAA AA A AAAAAAAAAAAAAAAA AA A AAAAAAAAAAAAAAAA AA A AAAAAAAAAAAAAAAA AA A AAAAAAAAAAAAAAAA AA A AAAAAAAAAAAAAAAA AA A AAAAAAAAAAAAAAAA AA A AAAAAAAAAAAAAAAA AA A AAAAAAAAAAAAAAAA AA A AAAAAAAAAAAAAAAA AA A AAAAAAAAAAAAAAAA AA A AAAAAAAAAAAAAAAA AAAAAAAA AAAAAAAAAAAAAAAA AA A AA AAAAAAAAAAAAAAAA AAAAAAAA AA
R2 R2B0 I1O1 R2B1 I1O2 R2B2 I1O3 R2B3 I1O4 R2B4 I1O5 R2B5 I2O1 R2B6 I2O2 R2B7 I2O3 R3B0 I2O4 R3B1 I2O5 R3B2 I3O1 R3B3 I3O2 R3B4 I3O3 R3B5 I3O4 R3B6 I3O5 R3B7 I4O1 R4B0 I4O2 R4B1 I4O3 R4B2 I4O4 R4B3 I4O5 R4B4 I5O1 R4B5 I5O2 R4B6 I5O3 R4B7 I5O4 Switch on MIC / LTX Switch on MIC / RXLS Switch on MIC / EPO Switch on MIC / AMREC Switch on MIC / AGCI Switch on DTMF / LTX Switch on DTMF / RXLS Switch on DTMF / EPO R3 Switch on DTMF / AMREC Switch on DTMF / AGCI Switch on LRX / LTX Switch on LRX / RXLS Switch on LRX / EPO Switch on LRX / AMREC Switch on LRX / AGCI Switch on AMPB / LTX R4 Switch on AMPB / RXLS Switch on AMPB / EPO Switch on AMPB / AMREC Switch on AMPB / AGCI Switch on AGCO / LTX Switch on AGCO / RXLS Switch on AGCO / EPO Switch on AGCO / AMREC 17 (29)
The switch matrix has 5 inputs and 5 outputs. Every pair of input and output except AGCO and AGCIN can be connected. The inputs and outputs used must be enabled. If 2 or more inputs are switched to an output, the sum of the inputs is available at the output. The inputs MIC and LRX have offset cancellers with a 3-dB corner frequency of 270 Hz. AMPB has a 60-kW input impedance. The TXO output has a digitallyprogrammable gain stage with a gain of 2, 3 to 9 dB depending on AGATX0 (LSB), AGATX1, AGATX2 (MSB) and a first order low-pass filter with 0.5 dB damping at 3300 Hz and 3 dB damping at 9450 Hz. The outputs RXLS, EPO and AMREC have a gain of 0 dB. The offset at the outputs of the matrix is less than 30 mV. If a switch is open, the path has a damping of more than 60 dB.
Table 3. Table of bits and corresponding switches Register No. Name Description
U4091BM
Sidetone System
LTX
8dB
LINE CK ZL
LRX
0-7dB
+ DIFF1 -
STO_DIFF
MOD
-10dB
RECIN STO
AGARX
AMP1
-10dB
9dB
AMP2
STOAMP
Sidetone balancing
LF STRC
STO 8.2 k
g
P
CTO 33 nF SL STC
f
14579
LF
P
SL
Figure 19. Principle circuit of the sidetone balancing
The SideTone Balancing (STB) has the task of reducing the crosstalk from LTX (microphone) to LRX (earpiece) in the frequency range of 0.3 to 3.4 kHz. The LTX signal is converted into a current in the MOD block. This current is transformed into a voltage signal (LINE) by the line impedance ZL. The LINE signal is fed into the summing amplifier DIFF1 via capacitor CK and attenuator AMP1. On the other hand the LTX buffered by STOAMP drives an external lowpass filter (RST, CST). The external lowpass filter and the internal STB have the transfer function drawn in the STB box. The amplified STB-output signal drives the negative input of the summing block. If both signals at the DIFF1 block are equal in level and phase, we have good suppression of the LTX signal. In this condition, the frequency and phase response of the STB block will represent the frequency curve on line. In real life the line impedance ZL varies strongly for different users. To obtain good suppression with one application for all different line impendances, the STB function is programmable.
The 3 programmable parameters are: 1. LF (gain at low frequency) LF has 15 programming steps of 0.5 dB. LF(0) gives -2 dB gain, LF(15) gives 5.5 dB gain.
STO_DIFF(LF) = (-10 dB - 2 dB + 0.5 dB LF + 9 dB) LTX
2. P (the pole position of the lowpass) The P adjustment has 31 steps. P(0) means the lowpass determined by the external application (RST, CST). The internally processed lowpass frequency is fixed by this equation 1 1.122 P f(P) 2 p CST RST
+
3. SL (sidetone slope; the pole frequency of the highpass) The SL has 3 steps. SL(0) is a lower frequency of the highpass. SL(3) is a higher frequency of the highpass. With SL, can be influenced the suppression at high frequencies.
18 (29)
Rev. A1, 02-Jun-98
Target Specification
U4091BM
-10dB -3dB ... -10dB and 7dB (NWT)
Offset cancel
32dB -23dB
ST Sidetone balancing
7dB0dB and 20dB (NWT)
SAO1
6dB
Line
VL
Offset cancel
1dB steps
LRX
RXLS 1.5dB steps
Loud- speaker SAO2
26dB -3dB and -10dB (DTMF)
RECO1
Earpiece
DTMF < -34dBm/ -32dBm >
DTMF generator MIC1 Handset micro- phone MIC2 Intercom micro- phone Answering machine MIC3
0dB 6dB steps 0dB 30dB12dB
Filter
7dB -48dB
DTMF < -24dBm/ -22dBm >
DTMF
EPO 1dB steps 9dB2dB
Switching matrix
Offset cancel
MIC LTX
RECO2
VL
8dB 1dB steps MOD
Line
1dB steps
0dB
AMPB
AMREC
0dB
AMPB
AMREC Answering machine
0dB
AGCO
AGCI
0dB
AGC
14578
Figure 20. Audio frequency signal management U4091BM
Absolute Maximum Ratings
AAAAA A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AAAAA AAAAA A A AA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAA AA
Line current DC line voltage Maximum input current Junction temperature Ambient temperature Storage temperature Total power dissipation, Tamb = 60C
Parameters
Symbol IL VL IRING Tj Tamb Tstg Ptot
Value 140 12 15 125 -25 to +75 -55 to +150 0.9
Unit mA V mA C C C W
Thermal Resistance
Junction ambient
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA
Rev. A1, 02-Jun-98 19 (29)
Parameters SSO44
Symbol RthJA
Value 70
Unit K/W
Target Specification
AAA A A A A A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA A AA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA A A A A A A A AA A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAA A A AA A A A A AA A A A AA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AA A A A A AA A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A AA A A A A AAA A A A A A A A AA A A A A AA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AAA A A A A A A A AA A A A A AA A A A A AAA A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A A AA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A AA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A A A A A A AA A A A A AA A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AA A A A AAA A A A A A A A AA A A A A AA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A AA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AA A A A A AA A A A AA A A A AA A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAA AA A A A A A A A AA A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAA AA A AA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A AA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAA AAA AAAAAAAA AAAAAAA A A AA A A A AA A A AAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAA AAAAAAAAAAAAAAAAAAAAAAAA AAA A A A A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A A A A A A AA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
f = 1 kHz, 0 dBm = 775 mVrms, IVMIC = 0.3 mA, IMP = 3 mA, RDC = 1.3 M, Tamb = 25C, Zear = 68 nF + 100 , ZM = 68 nF, resonator: f = 3.58 MHz, all bits in reset condition, unless otherwise specified.
Electrical Characteristics
U4091BM
20 (29) Parameters DC characteristics DC voltage drop-over circuit Test Conditions / Pins Symbol Min. Typ. Max.
IL = 2 mA 2.4 4.6 5.4 IL = 14 mA 5.0 VL IL = 60 mA 7.5 8.8 10.0 IL = 100 mA 9.4 Transmission amplifier, IL = 14 mA, VMIC = 2 mV, MICG[0:1] = 2, AGATX[0:2] = 7 ERX = ETX = ENMIC = ENSTBAL = I1O1 = I3O3 = 1, (GT = 48 dB) Transmit amplification MICG[0:1] = 2 GT 45.8 47AAAA 48.2 AGATX[0:2] = 7 Frequency response IL 14 mA, DGT -1 0 due to internal filters) f = 1 kHz to 3.4 kHz Gain change with IL = 14 to 100 mA DGT 0.5 current Gain deviation Tamb = -10 to +60C DGT 0.5 CMRR of microphone CMRR 60 80 amplifier Input resistance of Ri 50 MIC amplifier Input resistance of MICHF = 1 Ri 75 150 300 MIC3 amplifier Gain difference MICHF = 1 DGT 0.4 between MIC1, MIC2 to MIC3 Distortion at line IL 14 mA dt 2 VL = 700 mVrms Maximum output IL 19 mA, d < 5% VLmax 1.3 2.5 3.7 voltage VMIC = 10 mV CTXA = 1 F DBM5 = 0 DBM5 = 1 VLmax 3.8 5.0 6.2 VMIC = 20 m VMICOmax -5.2 MICG[0:1] = 3 Noise at line psophoIL 14 mA, MICG[0:1] = 2 no - 80 - 72 metrically weighted AGATX[0:2] = 7 Anti-clipping: CTXA = 1 mF ta 0.5 attack time tr each 3 dB overdrive 16 release time Gain at low operating IL = 8 mA, IMP = 1 mA GT 45.5 48.5 current RDC = 680 k VMIC = 0.5 mV IVMIC = 300 mA Distortion at low IL = 8 mA, IMP = 1 mA dt 5 operating current RDC = 680 k VMIC = 5 mV IVMIC = 300 mA
Target Specification
Rev. A1, 02-Jun-98 dBmp dBm dBm dBm Unit k k ms ms dB dB dB dB dB dB dB % % V Fig.
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA AA A A A A AA A A A A A A A AAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA A A A AAA A A A A A A AA A A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAA A AA A A A A AA A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA A A A AAA A A A A A A AA A A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA A A A A A AA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA A A A A A A AA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA A A A A AA A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA A A A A AAAAAAAAAAAAAAAAAAAAAAAAA A AA A A A A AA A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA A A A A AAA A A A A A A AA A A A A AA A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A A A A A AA A A A A AA A A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAA A AA A A A A AA A A A AA A A A AA A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAA A AA A A A A AA A A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAA AA AA A A A A AAA A A A A A A AA A A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA A A A A A A AA A A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAA AAAAAAAAAAAAA AAA AAAAAAAA A AA A A A AA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
Electrical Characteristics (continued)
Parameters Test Conditions / Pins Symbol Min. Typ. Max. Receiving amplifier IL = 14 mA, VGEN = 300 mV, ERX = ETX = ENMIC = ENSTBAL = I1O1 = I3O3 = 1, SL[0:1] = 0, LF[0:3] = 1, P[0:4] = 31, AGARX[0:2] = 0 Adjustment range of Single ended, GR -19 +17 receiving gain IL 14 mA, Mute = 1, EA[0:4] = 2 - 31 AGARX[0:2] = 0 - 7 Receiving Differential amplification AGARX[0:2] = 0 GR -1 0 1 EA[0:4] = 15 15 16 17 EA[0:4] = 31 Frequency response IL 14 mA, -1 DGRF 0 f = 1 kHz to 3.4 kHz Gain change with IL = 14 to 100 mA DGR 0.5 current Gain deviation Tamb = -10 to +60C DGR 0.5 Ear protection differen- IL 14 mA, EP 3 tial VGEN = 11 Vrms EA[0:4] = 21 MUTE suppression IL = 14 mA DGR 60 Output voltage IL = 14 mA 0.775 d < 2% differential Zear = 68 nF + 100 EA[0:4] = 11 Maximum output Zear = 100 Iout 4 current d < 2% EA[0:4] = 31 Receiving noise IL = 14 mA - 80 - 77 psophometrically Zear = 68 nF + 100 EA[0:4] = 21 weighted Sidetone suppression Z = 600 20 Output resistance Each output against GND Ro 10 Gain at low operating IL = 5 mA, IMP = 1 mA GR -2 0 2 current (receive only) IM = 300 mA VGEN = 200 mV RDC = 680 k, EA[0:4] = 21, ENMIC = ETX = I101 = 0 AC impedance IMPH = 0 Zimp 620 Zimp IMPH = 1 1040 Distortion at low IL = 8 mA, IMP = 1 mA dR 5 operating current VGEN = 400 mV RDC = 680kW EA[0:4] = 21 Adjustment step: AGARX[0:4] = 1 0.8 1 1.2 ear-piece amplifier Adjustment step: EA[0:4] = 1 0.8 1 1.2 AGARX
Rev. A1, 02-Jun-98 dBmp mAp Vrms dB Vrms Unit dB dB dB dB dB dB dB dB dB dB %
Target Specification
U4091BM
W W
W
21 (29) Fig.
AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AA A A A A AA A A A A A AAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AA A A A AAA A A A A A A A AA A A A A AA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A AA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AA A A A A AA A A A AA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AA A A A A AA A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AA A A A A AA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AA A A A AAAAAAAAAAAAAAAAAAAAAAAAA A A AA A A A A AA A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AA A A AAA A A A A A A A AA A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA A A A A A A A AA A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAA A A A A A A A AA A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AA A A A A A AA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A AA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A A A A A A AA A A A A AA A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A AA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA A A AA A A A AAA A A A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAA AAAAAAAAAAAAA AAA AAAAAAAA A A AA A A A AA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
mVpsoph
AA A AA A A A A A AAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A A A A A A A AA A A A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAA
Electrical Characteristics (continued)
U4091BM
Test Conditions / Pins Symbol Min. Typ. Max. AMPB RECO1/2 -16 EA[0:4] = 1 DTMF, IL = 14 mA, ETX = I201 = 1, AGATX[0:2] = 7, DTMFM[0:2] = 4, DTMFF[0:2] = 0 Max. level at line Sum level, 600 W, -5.1 -3.6 -2.1 DTMFM[0:2] = 5 DTMF level at line Sum level, 600 W, -7.6 -6.1 -4.6 (low gain) DTMFM[0:2] = 4 Pre-emphasis 600 W, DTMFF4 = 0 2 2.5 3 DTMFF4 = 1 3 3.5 4 Speaker amplifier, differential mode AMPB SAO1/2 ENSACL = ENSA = ENSAO = ENAM = I4O2 = 1, SA[0:4] = 31 Minimum line current No AC signal ILmin 8 for operation Gain from AMPB to VAMPB = 3 mV, IL = 15 mA, GSA 37 38 39 SAO SA[0:4] = 31 -8.5 SA[0:4] = 0 Adjustment step SA[0:4] = -1 1.3 1.5 1.7 speaker amplifier Output power single Load resistance: ended RL = 50 , d < 5% VAMPB = 20 mV, SE = 1 PSA 3 7 IL = 15 mA PSA IL = 20 mA 20 Max. output power Load resistance: PSA 200 differential RL = 50 , d < 5% VAMPB = 20 mV, SE = 0 VB = 5 V Output noise IL > 15 mA nSA 240 (input AMPB open) psophometrically weighted Gain deviation IL = 15 mA DGSA 1 Tamb = -10 to +60C Mute suppression IL = 15 mA, VL = 0 dBm, VSAO -60 VAMPB = 4 mV I4O2 = 0 Gain change with IL = 15 to 100 mA DGSA 1 current Gain change with IL = 15 mA DGSA -1 0 frequency f = 1 kHz to 3.4 kHz Attack time of 20 dB over drive tr 5 anti-clipping Release time of tf 80 anti-clipping Adjustment step of ENSAO = 0, SE = 1 -480 400 -320 charge current DLSCUR[0:1] = 1 Adjustment step of ENSAO = 0, SE = 0 320 400 480 discharge current DLSCUR[0:1] = 1
22 (29)
Parameters Gain for DTMF signal
Target Specification
Rev. A1, 02-Jun-98 dB dBm dBm dBm dBm dBm Unit mW mW mW mA
mA mA
ms ms
dB dB dB dB dB
Fig.
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Electrical Characteristics (continued)
Parameters Test Conditions / Pins Symbol Min. Typ. Charge current ENSAO = 0, SE = 1 ICHA -1.45 -1.2 Pin SAO2 LSCUR[0:1] = 3 Discharge current ENSAO = 0, SE = 0 IDIS 0.95 1.2 Pin SAO2 LSCUR[0:1] = 3 Microphone amplifier, VB = 5 V, VMIC = 2 mV, VMIC3 = 2 mV, ENMIC = ENAM = I1O4 = 1, MICHF = 0 Gain MIC amp.: MICG[0:1] = 0 18.6 19 MIC1/2 AMREC MICG[0:1] = 1 24.6 25 MICG[0:1] = 2 30.6 31 MICG[0:1] = 3 36.6 37 MIC3 AMREC MICHF = 1, MICG[0:1] = 3 36.6 37 Input suppression: MICG[0:1] = 0, MICHF = 0 60 MIC3 MIC1/2 MIC1/2 MIC3 MICHF = 1 60 Settling time 5 t, FOFFC = 0 offset-cancellers Settling time offset5 t, FOFFC = 1 cancellers in speed-up mode AGC for answering machine, AMPB AMREC, ENAM = ENAGC = I4O5 = I5O4 = 1 Nominal gain VAMPB = 5 mV 24 26 Max. output level VAMPB = 50 mV, d< 5% 240 300 Attack time 20 dB overdrive 2 Release time 45 Switching matrix, VL = 0, VB = 5 V, ENAM = I4O4 = 1, VAMPB = 1 Vrms Input impedance 50 60 AMPB Gain AMPB -0.4 0 AMREC Max. input level AMPB Max. output level AMREC Offset I4O4: 1 0 DVAMREC Mute switching matrix I4O4 = 0 60 Power-on reset VL = 0, VMP = 3.3 V, VB = 5 V, U4091 in power-down mode Power-on reset by VB = 4 V, ES = 4 V, VMPon 2.65 2.75 VMP threshold, VL or rise VMP VRING or ES high Power-on reset by VB VMP = 3 V, ES = 3 V, VBon 3.1 threshold, VL or rise VB VRING or ES high
Rev. A1, 02-Jun-98 VB- 600 mV 30 Max. -0.95 2.85 19.4 25.4 31.4 37.4 37.4 1.45 600 28 360 300 0.4 70 60 dB mVp ms ms Unit mA VPP mV dB mV mA k dB ms dB dB ms dB dB dB dB dB V V
Target Specification
U4091BM
23 (29) Fig.
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Electrical Characteristics (continued)
U4091BM
-1 1 Input leakage current 0 < Vi < VMP mA Pins INT, Output low 220 310 400 SDA (output mode) (resistance to GND) Switch for additional impedance (Pin IMPSW) VMP = 3.3 V, VB = 3 V Switch-off leakage 0 < Vi < VMP -2 2 mA IMPSW = 0 current Resistance to GND IMPSW = 1 30 50 W Max. current IMPSW = 1 -5 5 mA AFS acoustic feedback suppression, IL = 14 mA, VGEN = 300 mV, ERX = ETX = ENMIC = ENSTBAL = I1O1 = I3O3 = 1, SL[0:1] = 0, LF[0:3] = 1, P[0:4] = 31, AGARX[0:2] = 0 Adjustment range of IL 15 mA 0 50 dB attenuation Attenuation of transmit IL 15 mA, IINLDT = 0 mA DGT 48 50 52 dB gain IINLDR = 10 mA Attenuation of speaker IL 15 mA, IINLDT = 10 mA GSA 48 50 52 dB amplifier IINLDR = 0 mA Supply voltages, VMIC = 25 mV, Tamb = - 10 to + 60C VMP IL = 14 mA, RDC = 680 kW VMP 3.1 3.3 3.5 V IMP = 3 mA VMPS IL = 100 mA, RDC = inf., VMPS 5.7 V IMP = 0 mA VMIC IL 14 mA, RDC = 1.3 MW VMIC 1.5 4 V IM = 700 A VB IB = +20 mA, IL = 0 mA VB 5.5 6.3 V Ringing power converter, IMP = 1 mA, IM = 0 RIMPA = 500 kW Maximum output VRING = 20.6 V PSA 20 mW power ENSA = ENSAO = SE = 1
24 (29) Parameters Test Conditions / Pins Low-voltage interrupt VL = 0, VMP = 3.3 V, VB = 0 V VMP decreasing Decrease VMP until INT returns to high Power-off reset VL = 0, VMP = 3.3 V, VB = 0 V Low-voltage reset Decrease VMP until RESET returns to low Difference voltage VLVI - VLVR between low-voltage interrupt and reset Logical part VMP = 3.3 V, VB = 5 V Output impedance at OSCOUT Pins SCL, Low level SDA (input mode) High level Symbol VLVR VLVI
0.8 VMP
Target Specification
Min. 2.35 100 0.5 2.5 Typ. 2.45 150 2.6
0.2 VMP
Max.
2.55
1.0
2.7
Rev. A1, 02-Jun-98 Unit mV k V V V V Fig.
U4091BM
Electrical Characteristics (continued)
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6.3 20 0.8 7 7.7 24 1.2 6 V V V Adjustment steps threshold Input impedance VRING = 30 V 4 Z-diode voltage IRING = 15 mA VRINGmax 30.8 Serial bus SCL, SDA, AS, VMP = 3.3 V, RSDA = RSCL = RINT = 12 kW Input voltage SDA, SCL, INT ViBUS HIGH 3.0 LOW 0 Output voltage SDA Acknowledge LOW ISDA = 3 mA VO Clock frequency SCL fSCL Rise time SDA, SCL tr Fall time SDA, SCL tf Period of SCL HIGH HIGH tH 4.0 LOW LOW 4.7 tL Setup time Start condition tsSTA 4.7 Data 250 tsDAT Stop condition 4.7 tsSTOP Time space 1) 4.7 twSTA Hold time Start condition thSTA 4.0 DATA 0 thDAT 22 1 5 k V VDD 1.5 0.4 100 1 300 V V V kHz
Parameters Threshold
Test Conditions / Pins VRING: high to low low to high, RINGTH [0:3] = 0 low to high RINGTH [0:3] = 15 DRINGTH = 1
Symbol
Min.
Typ. 4.5
Max.
Unit V
Fig.
ms
ns
ms ms ms ms ms ms ms
ns
1)
This is a space of time where the bus must bee from data transmission and before a new transmission can be started
Bus Timing
SDA
twSTA tr tf thSTA
SCL
P S thSTA tL thDAT tH tsSTA thDAT tsSTOP P P = Stop, S = Start
Figure 21. Bus timing diagram
95 10122
Rev. A1, 02-Jun-98
25 (29)
Target Specification
Test Circuits
U4091BM
26 (29)
sin V + V V 3.58 MHz V + + PWL PWL A
Target Specification
Rev. A1, 02-Jun-98
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
Figure 22. Basic test circuit
U4091BM
1
2
3
4
5
6 V
7
8
9 10 C IND
10
11
12
13
14
15
16
17
18
19
20
21
22
W
+
+
R CD V 50
sin
sin
W
V
14597
V
V
Rev. A1, 02-Jun-98
PWL PWL 3.58 MHz + +
Target Specification
27 (29)
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
Figure 23. Test circuit for ringing
U4091BM
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21 BC 556
22 2.2 mH
68 nF V SD103A 50 W V VB
14600
U4091BM
VB
U4091BM
Package Information
Package SSO44
Dimensions in mm
18.05 17.80 9.15 8.65 7.50 7.30
2.35 0.3 0.8 16.8 44 23 0.25 0.10
0.25 10.50 10.20
technical drawings according to DIN specifications 13040
1
22
28 (29)
Rev. A1, 02-Jun-98
Target Specification
U4091BM
Ozone Depleting Substances Policy Statement
It is the policy of TEMIC Semiconductor GmbH to 1. Meet all present and future national and international statutory requirements. 2. Regularly and continuously improve the performance of our products, processes, distribution and operating systems with respect to their impact on the health and safety of our employees and the public, as well as their impact on the environment. It is particular concern to control or eliminate releases of those substances into the atmosphere which are known as ozone depleting substances ( ODSs). The Montreal Protocol ( 1987) and its London Amendments ( 1990) intend to severely restrict the use of ODSs and forbid their use within the next ten years. Various national and international initiatives are pressing for an earlier ban on these substances. TEMIC Semiconductor GmbH has been able to use its policy of continuous improvements to eliminate the use of ODSs listed in the following documents. 1. Annex A, B and list of transitional substances of the Montreal Protocol and the London Amendments respectively 2 . Class I and II ozone depleting substances in the Clean Air Act Amendments of 1990 by the Environmental Protection Agency ( EPA) in the USA 3. Council Decision 88/540/EEC and 91/690/EEC Annex A, B and C ( transitional substances ) respectively. TEMIC Semiconductor GmbH can certify that our semiconductors are not manufactured with ozone depleting substances and do not contain such substances.
We reserve the right to make changes to improve technical design and may do so without further notice. Parameters can vary in different applications. All operating parameters must be validated for each customer application by the customer. Should the buyer use TEMIC products for any unintended or unauthorized application, the buyer shall indemnify TEMIC against all claims, costs, damages, and expenses, arising out of, directly or indirectly, any claim of personal damage, injury or death associated with such unintended or unauthorized use. TEMIC Semiconductor GmbH, P.O.B. 3535, D-74025 Heilbronn, Germany Telephone: 49 ( 0 ) 7131 67 2831, Fax number: 49 ( 0 ) 7131 67 2423
Rev. A1, 02-Jun-98
29 (29)
Target Specification

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